View GAL18V10B-15LJN_7684005.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

gal18v10 high performance e 2 cmos pld generic array logic? 1 2 20 i/clki i i i i i vcc i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i gnd i/o/q i/o/q i/o/q i/o/q 4 6 8 9 11 13 14 16 18 1 10 11 20 i/clk i i i i i i i i/o/q gnd vcc i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q 5 15 gal18v10 top view gal 18v10 dip plcc i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/clk reset preset 8 8 8 8 10 10 8 8 8 8 olmc olmc olmc olmc olmc olmc olmc olmc olmc olmc i i i i i i i programmable and-array (96x36) copyright ? 2003 lattice semiconductor corp. all brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. lattice semiconductor corp., 5555 northeast moore ct., hillsboro, oregon 97124, u.s.a. november 2003 tel. (503) 268-8000; 1-800-lattice; fax (503) 268-8556; http://www.latticesemi.com 18v10_04 features ? high performance e 2 cmos ? technology ? 7.5 ns maximum propagation delay ? fmax = 111 mhz ? 5.5 ns maximum from clock input to data output ? ttl compatible 16 ma outputs ? ultramos ? advanced cmos technology ? low power cmos ? 75 ma typical icc ? active pull-ups on all pins ?e 2 cell technology ? reconfigurable logic ? reprogrammable cells ? 100% tested/100% yields ? high speed electrical erasure (<100ms) ? 20 year data retention ? ten output logic macrocells ? uses standard 22v10 macrocell architecture ? maximum flexibility for complex logic designs ? preload and power-on reset of registers ? 100% functional testability ? applications include: ? dma control ? state machine control ? high speed graphics processing ? standard logic speed upgrade ? electronic signature for identification description the gal18v10, at 7.5 ns maximum propagation delay time, com- bines a high performance cmos process with electrically eras- able (e 2 ) floating gate technology to provide a very flexible 20-pin pld. cmos circuitry allows the gal18v10 to consume much less power when compared to its bipolar counterparts. the e 2 technol- ogy offers high speed (<100ms) erase times, providing the ability to reprogram or reconfigure the device quickly and efficiently. by building on the popular 22v10 architecture, the gal18v10 eliminates the learning curve usually associated with using a new device architecture. the generic architecture provides maximum design flexibility by allowing the output logic macrocell (olmc) to be configured by the user. the gal18v10 olmc is fully com- patible with the olmc in standard bipolar and cmos 22v10 de- vices. unique test circuitry and reprogrammable cells allow complete ac, dc, and functional testing during manufacture. as a result, lattice semiconductor delivers 100% field programmability and function- ality of all gal products. in addition, 100 erase/write cycles and data retention in excess of 20 years are specified. functional block diagram pin configuration select devices have been discontinued. see ordering information section for product status.
specifications gal18v10 2 blank = commercial grade package power l = low power speed (ns) xxxxxxxx xx x x x device name _ p = plastic dip j = plcc gal18v10b gal18v10 ordering information commercial grade specifications part number description 1. discontinued per pcn #06-07. contact rochester electronics for available inventory. )sn(dp t) sn(us t) sn(oc t) am(cc i# gniredr oe gakcap 5. 765 . 55 11 01v81lag b-7 pl 1 pidcitsalpnip-02 511 01v81lag b-7 jl 1 cclpdael-02 0 177 5 11 01v81la gb1 -0p l pidcitsalpnip-02 511 01v81la gb1 -0j l cclpdael-02 5 180 15 11 01v81la gbp l51- pidcitsalpnip-02 511 01v81la gb j l 51- cclpdael-02 0 22 12 15 11 01v81la gbp l02- pidcitsalpnip-02 511 01v81la gbj l02- cclpdael-02 select devices have been discontinued. see ordering information section for product status.
specifications gal18v10 3 gal18v10 output logic macrocell (olmc) each of the macrocells of the gal18v10 has two primary functional modes: registered, and combinatorial i/o. the modes and the output polarity are set by two bits (so and s1), which are normally controlled by the logic compiler. each of these two primary modes, and the bit settings required to enable them, are described below and on the the following page. registered in registered mode the output pin associated with an individual olmc is driven by the q output of that olmc?s d-type flip-flop. logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). output tri-state control is available as an in- dividual product term for each olmc, and can therefore be defined by a logic equation. the d flip-flop?s /q output is fed back into the and array, with both the true and complement of the feedback available as inputs to the and array. note: in registered mode, the feedback is from the /q output of the register, and not from the pin; therefore, a pin defined as reg- istered is an output only, and cannot be used for dynamic i/o, as can the combinatorial pins. combinatorial i/o in combinatorial mode the pin associated with an individual olmc is driven by the output of the sum term gate. logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). out- put tri-state control is available as an individual product-term for each output, and may be individually set by the compiler as either ?on? (dedicated output), ?off? (dedicated input), or ?product-term driven? (dynamic i/o). feedback into the and array is from the pin side of the output enable buffer. both polarities (true and inverted) of the pin are fed back into the and array. the gal18v10 has a product term for asynchronous reset (ar) and a product term for synchronous preset (sp). these two prod- uct terms are common to all registered olmcs. the asynchronous reset sets all registered outputs to zero any time this dedicated product term is asserted. the synchronous preset sets all registers to a logic one on the rising edge of the next clock pulse after this product term is asserted. note: the ar and sp product terms will force the q output of the flip-flop into the same state regardless of the polarity of the output. therefore, a reset operation, which sets the register output to a zero, may result in either a high or low at the output pin, depending on the pin polarity chosen. the gal18v10 has a variable number of product terms per olmc. of the ten available olmcs, two olmcs have access to ten prod- uct terms (pins 14 and 15), and the other eight olmcs have eight product terms each. in addition to the product terms available for logic, each olmc has an additional product-term dedicated to out- put enable control. the output polarity of each olmc can be individually programmed to be true or inverting, in either combinatorial or registered mode. this allows each output to be individually configured as either active high or active low. ar sp d q q clk 4 to 1 mux 2 to 1 mux output logic macrocell (olmc) output logic macrocell configurations select devices have been discontinued. see ordering information section for product status.
specifications gal18v10 4 active high active low active high active low s 0 = 1 s 1 = 1 s 0 = 0 s 1 = 1 s 0 = 0 s 1 = 0 s 0 = 1 s 1 = 0 ar sp d q q clk ar sp d q q clk registered mode combinatorial mode select devices have been discontinued. see ordering information section for product status.
specifications gal18v10 5 dip and plcc package pinouts asynchronous reset (to all registers) 1 0036 . . . 0324 19 olmc s0 3456 s1 3457 18 17 16 15 14 13 12 11 9 0 4 8 12 16 20 24 28 32 olmc s0 3458 s1 3459 olmc so 3460 s1 3461 olmc s0 3462 s1 3463 olmc s0 3464 s1 3465 olmc s0 3466 s1 3467 olmc s0 3468 s1 3469 olmc s0 3470 s1 3471 olmc s0 3472 s1 3473 olmc s0 3474 s1 3475 0000 0360 . . . 0648 0684 . . . 0972 1008 . . . 1296 1332 . . . . 1692 2448 . . . 2736 1728 . . . . 2088 2124 . . . 2412 2772 . . . 3060 3096 . . . 3384 2 3 4 5 6 synchronous preset (to all registers) 3420 7 8 electronic signature 3476, 3477 ... ... 3538, 3539 l s b m s b byte 7 byte 6 byte 5 byte 4 byte 3 byte 2 byte 1 byte 0 8 8 8 8 10 10 8 8 8 8 gal18v10 logic diagram/jedec fuse map select devices have been discontinued. see ordering information section for product status.
specifications gal18v10b 6 commercial i cc operating power v il = 0.5v v ih = 3.0v l -7/-10/-15/-20 ? 75 115 ma supply current f toggle = 15mhz outputs open dc electrical characteristics over recommended operating conditions (unless otherwise specified) symbol parameter condition min. typ. 3 max. units v il input low voltage vss ? 0.5 ? 0.8 v v ih input high voltage 2.0 ? vcc+1 v i il 1 input or i/o low leakage current 0v v in v il (max.) ? ? ?100 a i ih input or i/o high leakage current 3.5v v in v cc ??10 a v ol output low voltage i ol = max. vin = v il or v ih ? ? 0.5 v v oh output high voltage i oh = max. v in = v il or v ih 2.4 ? ? v i ol low level output current ? ? 16 ma i oh high level output current ? ? ?3.2 ma i os 2 output short circuit current v cc = 5v v out = 0.5v t a = 25 c ?30 ? ?130 ma 1) the leakage current is due to the internal pull-up on all pins. see input buffer section for more information. 2) one output at a time for a maximum duration of one second. vout = 0.5v was selected to avoid test problems caused by tester ground degradation. characterized but not 100% tested. 3) typical values are at vcc = 5v and t a = 25 c absolute maximum ratings (1) supply voltage v cc ....................................... -0.5 to +7v input voltage applied ........................... -2.5 to v cc +1.0v off-state output voltage applied .......... -2.5 to v cc +1.0v storage temperature ................................. -65 to 150 c ambient temperature with power applied ......................................... -55 to 125 c 1. stresses above those listed under the ?absolute maximum ratings? may cause permanent damage to the device. these are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). recommended operating conditions commercial devices: ambient temperature (t a ) ............................. 0 to +75 c supply voltage (v cc ) with respect to ground ..................... +4.75 to +5.25v select devices have been discontinued. see ordering information section for product status.
specifications gal18v10b 7 t pd a input or i/o to comb. output ? 7.5 ? 10 ? 15 ? 20 ns t co a clock to output delay ? 5.5 ? 7 ? 10 ? 12 ns t cf 2 ? clock to feedback delay ? 3.5 ? 3.5 ? 7 ? 10 ns t su ? setup time, input or fdbk before clk 5.5 ? 6 ? 8 ? 12 ? ns t h ? hold time, input or fdbk after clk 0? 0? 0 ? 0 ?ns a maximum clock frequency with 90.9 ? 76.9 ? 55.5 ? 41.6 ? mhz external feedback, 1/(tsu + tco) f max 3 a maximum clock frequency with 111 ? 105 ? 66.7 ? 45.4 ? mhz internal feedback, 1/(tsu + tcf) a maximum clock frequency with 111 ? 105 ? 66.7 ? 62.5 ? mhz no feedback t wh ? clock pulse duration, high 4 ? 4 ? 6 ? 8 ? ns t wl ? clock pulse duration, low 4 ? 4 ? 6 ? 8 ? ns t en b input or i/o to output enabled ? 8 ? 10 ? 15 ? 20 ns t dis c input or i/o to output disabled ? 8 ? 9 ? 15 ? 20 ns t ar a input or i/o to asynch. reset of reg. ? 13 ? 13 ? 20 ? 20 ns t arw ? asynch. reset pulse duration 8 ? 8 ? 10 ? 15 ? ns t arr ? asynch. reset to clk recovery time 8 ? 8 ? 10 ? 15 ? ns t spr ? synch. preset to clk recovery time 10 ? 10 ? 10 ? 12 ? ns units param. test cond. 1 description 1) refer to switching test conditions section. 2) calculated from fmax with internal feedback. refer to fmax description section. 3) refer to fmax description section. symbol parameter maximum* units test conditions c i input capacitance 8 pf v cc = 5.0v, v i = 2.0v c i/o i/o capacitance 8 pf v cc = 5.0v, v i/o = 2.0v *characterized but not 100% tested. com com com com -7 min. max. -10 min. max. -15 min. max. -20 min. max. ac switching characteristics over recommended operating conditions capacitance (t a = 25 c, f = 1.0 mhz) select devices have been discontinued. see ordering information section for product status.
specifications gal18v10 8 input or i/o to output enable/disable registered output combinatorial output valid input input or i/o feedback t pd combinatorial output input or i/o feedback registered output clk valid input t su t co t h (external fdbk) 1/ f max t en t dis input or i/o feedback output clk ( w/o fdbk ) t wh 1/ f max t wl clock width registered output clk input or i/o feedback driving sp t su t h t co t spr registered output clk t arw t arr input or i/o feedback driving ar t ar f max with feedback clk registered feedback t cf t su 1/ f max (internal fdbk) synchronous preset asynchronous reset switching waveforms select devices have been discontinued. see ordering information section for product status.
specifications gal18v10 9 f max with internal feedback 1/( t su+ t cf) note: tcf is a calculated value, derived by sub- tracting tsu from the period of fmax w/internal feedback ( t cf = 1/ f max - t su). the value of t cf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. for example, the timing from clock to a combi- natorial output is equal to tcf + tpd. f max with no feedback note: f max with no feedback may be less than 1/( t wh + t wl). this is to allow for a clock duty cycle of other than 50%. note: f max with external feedback is cal- culated from measured tsu and tco. f max with external feedback 1/( t su+ t co) register logic array clk t su + t h test point c * l from output (o/q) under test +5v *c l includes test fixture and probe capacitance r 2 r 1 register logic array t co t su clk output load conditions (see figure) test condition r 1 r 2 c l a 300 390 50pf b active high 390 50pf active low 300 390 50pf c active high 390 5pf active low 300 390 5pf input pulse levels gnd to 3.0v input rise and -7/-10 2ns 10% ? 90% fall times -15/-20 3ns 10% ? 90% input timing reference levels 1.5v output timing reference levels 1.5v output load see figure 3-state levels are measured 0.5v from steady-state active level. clk register logic array t cf t pd f max descriptions switching test conditions select devices have been discontinued. see ordering information section for product status.
specifications gal18v10 10 electronic signature an electronic signature is provided in every gal18v10 device. it contains 64 bits of reprogrammable memory that can contain user- defined data. some uses include user id codes, revision numbers, or inventory control. the signature data is always available to the user independent of the state of the security cell. security cell a security cell is provided in every gal18v10 device to prevent unauthorized copying of the array patterns. once programmed, this cell prevents further read access to the functional bits in the device. this cell can only be erased by re-programming the de- vice, so the original configuration can never be examined once this cell is programmed. the electronic signature is always available to the user, regardless of the state of this control cell. latch-up protection gal18v10 devices are designed with an on-board charge pump to negatively bias the substrate. the negative bias is of sufficient magnitude to prevent input undershoots from causing the circuitry to latch. additionally, outputs are designed with n-channel pullups instead of the traditional p-channel pullups to eliminate any pos- sibility of scr induced latching. device programming gal devices are programmed using a lattice semiconductor- approved logic programmer, available from a number of manu- facturers (see the the gal development tools section). complete programming of the device takes only a few seconds. erasing of the device is transparent to the user, and is done automatically as part of the programming cycle. typical input current 1.0 2.0 3.0 4.0 5.0 -60 0 -20 -40 0 input voltage (volts) input current (ua) output register preload when testing state machine designs, all possible states and state transitions must be verified in the design, not just those required in the normal machine operations. this is because certain events may occur during system operation that throw the logic into an illegal state (power-up, line voltage glitches, brown-outs, etc.). to test a design for proper treatment of these conditions, a way must be provided to break the feedback paths, and force any desired (i.e., illegal) state into the registers. then the machine can be sequenced and the outputs tested for correct next state conditions. the gal18v10 device includes circuitry that allows each registered output to be synchronously set either high or low. thus, any present state condition can be forced for test sequencing. if necessary, approved gal programmers capable of executing test vectors perform output register preload automatically. input buffers gal18v10 devices are designed with ttl level compatible input buffers. these buffers have a characteristically high impedance, and present a much lighter load to the driving logic than bipolar ttl devices. the input and i/o pins also have built-in active pull-ups. as a result, floating inputs will float to a ttl high (logic 1). however, lattice semiconductor recommends that all unused inputs and tri-stated i/o pins be connected to an adjacent active input, vcc, or ground. doing so will tend to improve noise immunity and reduce icc for the device. select devices have been discontinued. see ordering information section for product status.
specifications gal18v10 11 typical input typical output vcc pin vcc vref active pull-up circuit esd protection circuit esd protection circuit vcc pin vcc pin vref tri-state control active pull-up circuit feedback (to input buffer) pin feedback data output (vref typical = 3.2v) (vref typical = 3.2v) circuitry within the gal18v10 provides a reset signal to all reg- isters during power-up. all internal registers will have their q outputs set low after a specified time (tpr, 1 s max). as a result, the state on the registered output pins (if they are enabled) will be either high or low on power-up, depending on the programmed polarity of the output pins. this feature can greatly simplify state machine design by providing a known state on power-up. be- cause of the asynchronous nature of system power-up, some conditions must be met to provide a valid power-up reset of the device. first, the v cc rise must be monotonic. second, the clock input must be at static ttl level as shown in the diagram during power up. the registers will reset within a maximum of tpr time. as in normal system operation, avoid clocking the device until all input and feedback path setup times have been met. the clock must also meet the minimum pulse width requirements. vcc (min.) t pr internal register reset to logic "0" device pin reset to logic "1" t wl t su device pin reset to logic "0" vcc clk internal register q - output active low output register active high output register power-up reset input/output equivalent schematics select devices have been discontinued. see ordering information section for product status.
specifications gal18v10 12 normalized tpd vs vcc supply voltage (v) normalized tpd 0.8 0.9 1 1.1 1.2 4.50 4.75 5.00 5.25 5.50 pt h->l pt l->h normalized tco vs vcc supply voltage (v) normalized tco 0.8 0.9 1 1.1 1.2 4.50 4.75 5.00 5.25 5.50 rise fall normalized tsu vs vcc supply voltage (v) normalized tsu 0.8 0.9 1 1.1 1.2 4.50 4.75 5.00 5.25 5.50 pt h->l pt l->h normalized tpd vs temp temperature (deg. c) normalized tpd 0.7 0.8 0.9 1 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 pt h->l pt l->h normalized tco vs temp temperature (deg. c) normalized tco 0.7 0.8 0.9 1 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 rise fall normalized tsu vs temp temperature (deg. c) normalized tsu 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 -55 -25 0 25 50 75 100 125 pt h->l pt l->h delta tpd vs # of outputs switching number of outputs switching delta tpd (ns) -2 -1.5 -1 -0.5 0 12345678910 rise fall delta tco vs # of outputs switching number of outputs switching delta tco (ns) -2 -1.5 -1 -0.5 0 12345678910 rise fall delta tpd vs output loading output loading (pf) delta tpd (ns) -4 -2 0 2 4 6 8 10 0 50 100 150 200 250 300 rise fall delta tco vs output loading output loading (pf) delta tco (ns) -4 -2 0 2 4 6 8 10 0 50 100 150 200 250 300 rise fall gal18v10b: typical ac and dc characteristic diagrams select devices have been discontinued. see ordering information section for product status.
specifications gal18v10 13 vol vs iol iol (ma) vol (v) 0 0.25 0.5 0.75 1 0 10203040 voh vs ioh ioh(ma) voh (v) 0 1 2 3 4 5 0 102030405060 voh vs ioh ioh(ma) voh (v) 3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 01234 normalized icc vs vcc supply voltage (v) normalized icc 0.8 0.9 1 1.1 1.2 4.50 4.75 5.00 5.25 5.50 normalized icc vs temp temperature (deg. c) normalized icc 0.8 0.9 1 1.1 1.2 -55 -25 0 25 50 75 100 125 normalized icc vs freq. frequency (mhz) normalized icc 0.8 0.9 1 1.1 1.2 1.3 1.4 0 25 50 75 100 delta icc vs vin (1 input) vin (v) delta icc (ma) 0 1 2 3 4 5 6 7 8 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 input clamp (vik) vik (v) iik (ma) -120 -100 -80 -60 -40 -20 0 -2.00 -1.50 -1.00 -0.50 0.00 gal18v10b: typical ac and dc characteristic diagrams select devices have been discontinued. see ordering information section for product status.
specifications gal18v10 14 normalized icc vs. temperature ambient temperature (c) normalized icc 0.7 0.8 0.9 1 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 icc vs. temperature isb vs. temperature 4 i oh vs. v oh v oh (v) i oh (ma) 0 -50 -100 -150 01 23 0 50 100 150 200 250 012 3 4 i ol vs. v ol v ol (v) i ol (ma) delta tpd vs. output loading output loading capacitance (pf) delta tpd (ns) -2 0 2 4 6 8 10 0 100 200 300 400 normalized icc vs. vcc supply voltage (v) normalized icc 0.7 0.8 0.9 1 1.1 1.2 1.3 4.5 4.75 5 5.25 5.5 delta tpd vs. # of outputs switching # of outputs delta tpd (ns) -3 -2 -1 0 0 max. - 8 max. - 4 max. normalized tco vs. temperature ambient temperature (c) normalized tco 0.7 0.8 0.9 1 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 normalized tsu vs. temperature ambient temperature (c) normalized tsu 0.7 0.8 0.9 1 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 normalized tpd vs. temperature ambient temperature (c) normalized tpd 0.7 0.8 0.9 1 1.1 1.2 1.3 -50 -25 0 25 50 75 100 125 normalized tsu vs. vcc supply voltage (v) normalized tsu 0.7 0.8 0.9 1 1.1 1.2 1.3 4.5 4.75 5 5.25 5.5 pt l -> h pt h -> l normalized tco vs. vcc supply voltage (v) normalized tco 0.7 0.8 0.9 1 1.1 1.2 1.3 4.5 4.75 5 5.25 5.5 0.7 0.8 0.9 1 1.1 1.2 1.3 4.5 4.75 5 5.25 5.5 pt l -> h pt h -> l normalized tpd vs. vcc supply voltage (v) normalized tpd gal18v10b: typical ac and dc characteristic diagrams select devices have been discontinued. see ordering information section for product status.

▲Up To Search▲

Price & Availability of GAL18V10B-15LJN

	To Download GAL18V10B-15LJN Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .